Simulated data Generation, Transfer for the Testing of Layered Compression Coder ASIC Design using Scaleable Algorithm

Abstract

Our paper presents the procedure of dealing with pixel data for the ASIC using scalable algorithm and effectiveness of the image data generated for the simulation and testing of Layered Image Compression Chip. Data acquiring technique from external file is not only useful for our ASIC but also very handy for any other kind of ASIC whose requirement is to get generated representing the actual input video data. Actual video data may of format BT 656, or from some other source like Philips device 7114. Our paper presents the co-design of hardware VHDL and software like C or C++ to generate the input test vectors to verify the working of first module of Chip architecture. Large input data for testing, which is nearly impossible to be put manually. The problem of data input vectors is practically encountered while designing the chip.