A Compact Implementation of AES S-BOX Based on Dual Basis

Abstract

In the AES, it usually made up of four parts: AddRoundKey (ARK), SubBytes (SB), ShiftRows (SR), and MixColumns (MC). Among them, AddRoundKey, ShiftRows, and MixColumns are both linear operations, SubBytes is a nonlinear operation, which is the most complicated calculation. Moreover, S-box operations are also used in DES and SM4, so it has important research significance. Area optimization is particularly important in some chips with small area requirements. In order to reduce the hardware complexity, the finite field operation of the AES S-box is generally mapped to the composite field. At the same time, the design of the circuit using the dual basis will be smaller. In this paper, we propose an optimized design for the S-box in AES, which is mainly optimized for circuit area. The S-box is designed by using dual basis, and the circuit is simplified by AND-XOR array structure, so as to achieve the characteristics of small area. Compared with the previous works, the S-Box designed in this paper has a smaller area, which is 17.76% smaller than the previous S-Box. Compared to other basis, the S-Box are 29.87% and 25.34% smaller than that of the polynomial basis and normal basis respectively.