Three stage 2-D discrete wavelet transform using modified vedic multiplier

Abstract

The various 1-D and 2-D DWT architectures that exist in the literature are Row-column, parallel filter, folded, flipping and recursive structures. The architectures vary with respect to the computational and hardware requirement, the memory required to store the input image, and the intermediate coefficients. The main objective of this research work is to derive efficient VLSI architectures, for the hardware implementation of the DWT, using Vedic multiplier and improving the hardware complexities and speed of existing architectures.