A 5.37mW 10b 200MS/s dual-path pipelined ADC

Abstract

The opamps in a switched-capacitor (SC) pipelined ADC provide the functions of sample-and-hold, residue generation, and residue amplification [1,2]. High-performance opamps that meet the requirements for dc gain, speed, and signal range usually consume large power. We propose a scheme where the residue amplification is performed first by a coarse amplifier (CA), and then by a fine amplifier (FA). The CA generates a large-swing output that may not be accurate due to low dc gain and slow speed. Subsequently, the FA produces a small-swing output that stands as the error of the CA. The requirements for the CA and FA are different. They can be designed and optimized separately, resulting in low power dissipation. We report a 10b SC pipelined ADC to demonstrate this technique. Fabricated in 65nm CMOS, this ADC achieves 56.7dB SNDR at 200MS/s sampling rate, and consumes 5.37mW from a 1V supply.