The acceleration of VHDL simulation by classifying events

Abstract

The performance and efficiency of event-driven simulations, such as VHDL and Verilog simulation, depend on the number of events that occur during the simulation. In this paper, we classify events into two categories, sensitive events and insensitive events, according to the necessity of simulations, and implement the optimization methodology that eliminates unnecessary simulations caused by the insensitive events. Five experiments show that optimized VHDL programs run much faster than the original ones.