A yield-driven near-threshold 8-T SRAM design with transient negative bit-line scheme

Abstract

Increasing process variation and logic delay can significantly degrade the write-ability of near-threshold SRAM cells. In this paper, taking 8-T cell as an example, a transient NBL scheme is adopted to improve the write-ability of SRAM by using a transient negative bit-line voltage at the start of the word-line pulse without complicated on-chip control circuits, which greatly simplifies the design and effectively enhance the write ability. Meanwhile, we draw support from the efficient form of importance sampling and boundary searching methods in order to get our design guide for a better yield. Statistical simulations with a 40nm technology verify the design methodology. Array-level 8-T SRAM design can work under near-threshold Vdd with good performance and acceptable failure rate.