A 4Gb/s 1:16 DEMUX using an all-static 0.18-/spl mu/m CMOS logic

Abstract

This paper introduces a design for a 4Gb/s half rate 1:16 DEMUX based on 0.18 /spl mu/m CMOS technology using only static CMOS logic. A new sizing methodology is used to minimize the power consumption. The power consumption is reduced several times compared to recently published results with the delay power product also reduced by 33%.