{"title":"Current Control and FPGA–Based Real–Time Simulation of Grid–Tied Inverters","authors":"S. Carpiuc, Matthias Schiesser, C. Villegas","doi":"10.23919/EPE20ECCEEurope43536.2020.9215961","DOIUrl":null,"url":null,"abstract":"In this paper, the current controller synthesis and real–time testing in a grid–tied inverter system is discussed. The current loops are implemented using an observer–based linear quadratic regulator. The disturbance observer is employed to ensure zero steady state error in the presence of model uncertainties. A simulation model implemented in Simscape™ Electrical™ is used to evaluate the control algorithm in real–time on a Speedgoat real–time system with a field–programmable gate array FPGA board. The results show the effectiveness of the proposed solution.","PeriodicalId":241752,"journal":{"name":"2020 22nd European Conference on Power Electronics and Applications (EPE'20 ECCE Europe)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 22nd European Conference on Power Electronics and Applications (EPE'20 ECCE Europe)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/EPE20ECCEEurope43536.2020.9215961","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
In this paper, the current controller synthesis and real–time testing in a grid–tied inverter system is discussed. The current loops are implemented using an observer–based linear quadratic regulator. The disturbance observer is employed to ensure zero steady state error in the presence of model uncertainties. A simulation model implemented in Simscape™ Electrical™ is used to evaluate the control algorithm in real–time on a Speedgoat real–time system with a field–programmable gate array FPGA board. The results show the effectiveness of the proposed solution.