A 28GHz High-Efficiency Outphasing PA with Dynamic Impedance Compensation in 40nm CMOS

Abstract

This paper describes the design of a 28GHz high-efficiency outphasing power amplifier (PA) in a 40nm CMOS process. A capacitance neutralization technique and a dynamic impedance component to compensate the imaginary part of the impedance are proposed, which greatly increase the power efficiency in different phases. Using 1V supply in a common-source driver and 1.8V supply in the cascode PA, the PA achieves a simulated saturated output power of 23dBm with 47.4% power-added efficiency(PAE ) when the phase is 35°. The PAE at 6dB back off (PBO) from saturation is 21% when the phase is 20°.