Optimization of modular reduction procedure in RSA algorithm implementation on assembler of TMS320C54x signal processors

Abstract

Possible optimization techniques for the modular reduction procedure of RSA algorithm realization on assembler of Texas Instruments TMS320C54x family of signal processors are considered. Besides a standard dividing algorithm with a remainder, a reciprocal value method and Montgomery's procedure are considered. Obtained results show that the best results are obtained by using Montgomery's approach for modular reduction in the RSA algorithm and also show that the TMS320C54x family of signal processors is suitable for the RSA algorithm realization. Therefore, they are proposed for realization of some coprocessor module in computer networks with "client-server" architecture requiring public-key cryptographic applications.