FPGA-based programmable digital PLL with very high frequency resolution

2011 18th IEEE International Conference on Electronics, Circuits, and Systems Pub Date : 2011-12-01 DOI:10.1109/ICECS.2011.6122290

J. Bouloc, L. Nony, C. Loppacher, W. Rahajandraibe, F. Bocquet, Lakhdar Zaïd

引用次数: 3

Abstract

A FPGA-based tunable all-digital control system featuring high resolution all-digital PLL is presented. The whole system has been designed under Simulink environment and synthesized with QuartusII. The system can achieve very high frequency resolution (0.1Hz) within a frequency range of 20kHz to 60MHz.

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基于fpga的可编程数字锁相环，具有很高的频率分辨率

提出了一种基于fpga的高分辨率全数字锁相环可调全数字控制系统。整个系统在Simulink环境下进行了设计，并使用QuartusII进行了综合。该系统可以在20kHz至60MHz的频率范围内实现非常高的频率分辨率(0.1Hz)。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2011 18th IEEE International Conference on Electronics, Circuits, and Systems

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