Performance Evaluation of RISC-based SoC Platforms in Network Processing Applications

Abstract

In this paper, results of a simulative performance evaluation of RISC-based SoC platforms for networking applications are presented. We use our SystemC simulation environment that is calibrated with a reference implementation on an FPGA-based prototyping environment, consisting of a single RISC-CPU, memory system, Ethernet MAC and an autonomous DMA engine. In order to achieve precise results, a real IP stack has been profiled. Starting with an analysis of the reference scenario, two approaches for improvements are investigated. At first, hardware assists are added, which offload the CPU from compute-intensive bit-level manipulations. Second, the concept of flexible processing paths as proposed in FlexPath NP with AutoRoute is evaluated, in which some part of the traffic can bypass the central CPU cluster. For each of the three scenarios the maximum throughput is determined, and the improvements and limitations of each solution are discussed. It can be shown that a FlexPath NP achieves up to 2.5 times the throughput of the unoptimized reference scenario under realistic traffic assumptions