Evaluating a New RRAM Manufacturing Test Strategy

Abstract

Memristive devices represent a promising candidate to complement the CMOS technology due to their ability to overcome CMOS device technology limits as well as to implement not only memory but also computing elements. These characteristics make the implementation of emerging applications with strict constraints in terms of performance, area and power consumption possible. However, the adoption of these novel devices depends on being able to guarantee their quality after manufacturing. High-volume manufacturing tests pose significant challenges in terms of fault detection capability, test time as well as implementation overheads. In this context, this paper proposes a new implementation Design-for-Testability (DfT) strategy to test Resistive Random Access Memories (RRAMs). A case study based on a RRAM was implemented using the 28nm TSMC technology library and validated through electrical simulations. The new DfT strategy was evaluated with respect to its ability to detect unique and conventional faults. Finally, the paper presents a discussion about the introduced overheads and compares the proposed approach with state-of-the-art related to RRAM manufacturing test strategies.