CMOS RF: (still) no longer an oxymoron

Abstract

As CMOS continues to evolve along predicted trajectories, its suitability for RF applications only improves. Peak device f/sub T/ is /spl sim/40 GHz for 0.25 /spl mu/m technology and should double roughly every three years if established trends continue. The growing number of interconnect layers benefits passive components as well, such as lateral flux (e.g., fractal) capacitors, accumulation-mode varactors, and shielded inductors and transformers. Coplanar waveguides of reasonable quality are enabled also, and were recently used in a distributed amplifier with a 23 GHz unity-gain frequency, and in a 17 GHz distributed oscillator. Device F/sub min/ is well under 0.5 dB at 1-2 GHz, allowing practical LNA NFs in the /spl sim/1 dB range on <10 mW of power, while new insights into device noise scaling have eased concerns about hot carrier noise enhancement. Exploitation of a new phase noise theory has allowed a 1.8 GHz oscillator to exhibit under -121 dBc/Hz phase noise @600 kHz offset, with on-chip spiral inductors and 6 mW of power, by using symmetry to suppress the effect of 1/f device noise. The 17 GHz distributed oscillator also achieves a phase noise better than -110 dBc/Hz @ 1 MHz on 52 mW of power. These developments have most recently resulted in a 0.25 /spl mu/m 5 GHz LNA/mixer/synthesizer that exhibits 5 dB overall NF and -2 dBm IIP3 on 45 mW of power.