Verification of asynchronous circuits using time Petri net unfolding

Abstract

This paper describes a novel approach to timing analysis and verification of asynchronous circuits with bounded delays. The method is based on the time-driven unfolding of a time Petri net model of a circuit. Each reachable state, together with its timing constraints is represented implicitly. Our method is used to verify freedom from hazards in asynchronous circuits consisting of micropipeline components and logic gates.