Visual analytics support for the SOI VLSI layout design for multiple patterning technology

Abstract

In the paper, we discuss visualization techniques for SOI VLSI layout design. Our goal is visual analytics support of time-consuming SOI VLSI layout design process. Our analytics are based on graph models for VLSI layout representation. We propose classification and clustering approaches for data visualization. We illustrate our approach for contradictions visualization for multiple patterning technology case study.