Design of Highly Reliable Fault Backtracking Calculation for Space Applications

Abstract

The design architecture of backtracking calculation control processing for space large manipulator control is proposed. SRAM-type FPGA is used to build the hardware full three-mode computing core, and the processor architecture is designed based on FPGA. The register value and cache access value of the single instruction calculation process of the three computing processors are used to compare the three modes in the anti-fuse FPGA. At the same time, the results of three computing processors were compared by SPARC CPU. Fault backtracking calculation control, when a single computing module occurs an error, first detect the instruction execution position of the faulty module, and then carry out register-level data recovery for the faulty module, and restore to the instruction before the fault to accelerate the operation to complete the “backtracking” process, until the other two modules complete the calculation synchronization. According to the theoretical derivation and analysis, it is clear that under the linear increasing detection window, the maximum time of fault recovery is only related to the three-mode ratio transmission rate. According to this conclusion, the hardware digital logic design of the key modules of fault detection and recovery is carried out. The overall structure is simple and easy to implement, digital logic only occupies less than 100,000 logic gates. Compared with traditional methods, the fault recovery efficiency is improved by at least 90%.