Implementation of a decoder based on low-density parity-check code for 8 bit logical ALU

2017 8th Annual Industrial Automation and Electromechanical Engineering Conference (IEMECON) Pub Date : 2017-08-01 DOI:10.1109/IEMECON.2017.8079598

Dibyendu Deogharia, Jayanta Bhattacharya, Sutapa Ray, Sulagno Roy, Swetaki Chatterjee, Abhishek Lahiri, Debarpita Ray, Arindam Nandi, Sunetra Bhattacharyya, Ranjan Kumar Kush, Y. Prakash

引用次数: 0

Abstract

A Decoder working on the logic of LDPC is designed for a 8 bit Logical ALU. The Simulation has been done to minimize the Voltage Leakage and Maximum throughput.

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基于低密度奇偶校验码的8位逻辑ALU解码器的实现

针对8位逻辑ALU设计了一种基于LDPC逻辑的解码器。仿真已经完成，以尽量减少漏电压和最大吞吐量。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2017 8th Annual Industrial Automation and Electromechanical Engineering Conference (IEMECON)

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