A 2×25Gb/s 20mW serializing transmitter with 2.5:1 multiplexers in 40nm technology

2016 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2016-04-25 DOI:10.1109/VLSI-DAT.2016.7482532

Bo-Jing Lin, W. Chang, Tai-Cheng Lee

引用次数: 0

Abstract

A low-power serializing transmitter is proposed by using a 2.5:1 multiplexer. Owing to its fractional multiplexing operation, only a single clock is needed to simplify the clock generator design as well as hardware cost. Fabricated in a 40 nm CMOS technology, the transmitter can generate 2-channel 25-Gbps signals. The transmitter consumes only 24 mW from a 0.9-V power supply.

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一款2×25Gb/s 20mW串行发射机，采用2.5:1 40nm多路复用技术

提出了一种采用2.5:1多路复用器的低功耗串行发射机。由于其分式多路复用操作，因此只需要一个时钟，从而简化了时钟发生器的设计，降低了硬件成本。该发射器采用40纳米CMOS技术制造，可产生2通道25 gbps信号。发射机仅消耗24兆瓦的0.9 v电源。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2016 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)

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