Thermal Stress Study of 3D IC Based on TSV and Verification of Thermal Dissipation of STI

Abstract

With the continuous progress of chip integration, the three-dimensional integration technology based on silicon through-hole (TSV) has emerged and become one of the key technologies to achieve high-density system integration. However, its process size and interconnect technology directly lead to severe thermal reliability problems, so it becomes urgent to study the thermal characteristics of TSV arrays in 3D integrated circuits. In this paper, ANSYS Workbench is used to analyze the model for thermal stress. The effects of the diameter, height, spacing and filling material of the TSV on the overall thermal stress of the model were investigated using orthogonal table experiments. The orthogonal experimental analysis table was made based on the horizontal factor table of TSV, and the corresponding thermal stress values were obtained. The data results were analyzed using extreme difference analysis to determine the optimal combination of parameters. And this set of parameters is used as the basis for further analysis. In recent years some experts and scholars proposed the Shallow Trench Isolation Technology (STI), which is an effective method to reduce thermal stress. Using the previously selected set of data, simulation analysis is performed in Workbench to compare and verify the results. The analysis of the experimental results shows that the largest factor affecting the thermal stress of the TSV-based 3D IC is the filling material of the TSV, followed by the pitch of the TSV, the diameter of the TSV, and the smallest is the height of the TSV. Comparing the results of the experimental group shows that STI has a greater improvement on the heat deformation of the model and a significant reduction in its maximum stress, indicating that STI has a more significant improvement on the thermal stress of the TSV -based 3D integrated circuit.