Power supply noise reduction using additional resistors

Abstract

For high performance chips power noise issues become more prominent. In this paper power supply noise is damped with additional resistors in the impedance path between the package and the on-chip power distribution. Therefore, this path is split into several paths with different resistors. A distributed 2D signal line on-chip model in a simulated annealing schedule is utilized to find the appropriate resistors. The amount of noise reduction and the necessary voltage offset to overcome the additional IR drop has been investigated in several simulations. Further, the influence of splitting the power supply path only into very few different paths has been investigated.