A 20nm 1.8V 8Gb PRAM with 40MB/s program bandwidth

2012 IEEE International Solid-State Circuits Conference Pub Date : 2012-04-03 DOI:10.1109/ISSCC.2012.6176872

Youngdon Choi, I. Song, Mu-Hui Park, Hoeju Chung, Sang-whan Chang, B. Cho, Jinyoung Kim, Younghoon Oh, D. Kwon, Jung Sunwoo, Junho Shin, Yoohwan Rho, Changsoo Lee, M. Kang, Jaeyun Lee, Yongjin Kwon, Soehee Kim, Jaewhan Kim, Yong-jun Lee, Qi Wang, Sooho Cha, Sujin Ahn, H. Horii, Jaewook Lee, KiSeung Kim, Han-Sung Joo, Kwangjin Lee, Yeong-Taek Lee, Jei-Hwan Yoo, G. Jeong

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引用次数: 318

Abstract

Phase-change random access memory (PRAM) is considered as one of the most promising candidates for future memories because of its good scalability and cost-effectiveness [1]. Besides implementations with standard interfaces like NOR flash or LPDDR2-NVM, application-oriented approaches using PRAM as main-memory or storage-class memory have been researched [2-3]. These studies suggest that noticeable merits can be achieved by using PRAM in improving power consumption, system cost, etc. However, relatively low chip density and insufficient write bandwidth of PRAMs are obstacles to better system performance. In this paper, we present an 8Gb PRAM with 40MB/s write bandwidth featuring 8Mb sub-array core architecture with 20nm diode-switched PRAM cells [4]. When an external high voltage is applied, the write bandwidth can be extended as high as 133MB/s.

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20nm 1.8V 8Gb PRAM，程序带宽40MB/s

相变随机存取存储器(PRAM)因其良好的可扩展性和成本效益被认为是未来存储器最有前途的候选者之一[1]。除了使用NOR闪存或LPDDR2-NVM等标准接口实现外，还研究了使用PRAM作为主存或存储类内存的面向应用的方法[2-3]。这些研究表明，使用PRAM可以在降低功耗、降低系统成本等方面取得显著的成效。然而，相对较低的芯片密度和不足的写带宽是阻碍更好的系统性能。在本文中，我们提出了一个具有40MB/s写入带宽的8Gb PRAM，该PRAM采用20nm二极管开关PRAM单元，具有8Mb子阵列核心架构[4]。当外加高压时，写带宽可扩展到133MB/s。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2012 IEEE International Solid-State Circuits Conference

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